The present disclosure relates to a semiconductor memory device, and more particularly relates to a semiconductor memory device in which bit lines have a hierarchical structure.
Nowadays, memories built in systems on chip (SOCs) have their storage capacity further increased to have even higher operating speeds. As the storage capacity of those memories is increased, however, the number of memory cells to be connected to a single bit line also needs to be increased, which imposes a heavier and heavier load capacity on each bit line, thus inhibiting the memory cells from further increasing their operating speeds as required. Thus, a hierarchical bit line structure has been proposed as a known technique for cutting down the bit line capacity (see, for example, Japanese Patent No. 5019579). In the hierarchical bit line structure, bit lines are divided into multiple groups to be assigned to a plurality of memory banks, and memory cells in each of those memory banks are connected to a pair of local bit lines, which are further connected to a global bit line with the potential difference between the two bit lines amplified by a differential amplifier.
As another example using such a hierarchical bit line structure, a semiconductor memory device configured to read data using a single global bit line is disclosed in, for example, Japanese Patent No. 5178182. In this semiconductor memory device, one of the two outputs of a differential amplifier is connected to an inverter, the output of which is connected to the gate of a transistor that is connected between the global bit line and the ground, and data is read by sensing a variation in the potential of the global bit line. This semiconductor memory device needs a smaller number of global bit lines, and therefore, may reduce the amount of leakage current to flow and cut down the overall circuit area on the chip.
The semiconductor memory device disclosed in Japanese Patent No. 5178182, however, has the following drawbacks. Specifically, in general, when the potential difference between a pair of local bit lines is amplified by a differential amplifier, one of the two bit lines that has the higher potential is induced to have its potential somewhat lowered toward the Low potential level. As a result, the output level of the inverter that should be Low is raised to a High potential level to turn the transistor ON unintentionally. Thus, data may be read erroneously on the global bit line. Particularly if the inverter has varying threshold values such that the level of its input is easily determined to be Low or if there is little potential difference between the pair of bit lines, there are higher chances of the storage device operating erroneously.
In addition, while data is going to be read using a single global bit line, the global bit line may be precharged to the High level, for example, during the read operation, and a potential level of the global bit line is determined by an output circuit at an arbitrary point in time. In this case, if the potential of the global bit line has decreased to a lower level, the drivability of the output circuit may deteriorate too much to have the output data reset normally by the output circuit.
Furthermore, when a read operation is performed, the global bit line is no longer precharged, and therefore, becomes floating. In this case, if a plurality of memory banks are connected to the global bit line, then a plurality of transistors are connected to the global bit line. Thus, the global bit line that should have the High potential level is discharged due to the leakage current flowing from those transistors. As a result, the storage device may operate erroneously.
Moreover, since an inverter is connected to one of each pair of local bit lines, the load capacities of respective connection nodes between the pair of local bit lines and the differential amplifier are so imbalanced that the differential amplifier tends to operate erroneously, which is another concern about the conventional storage device.
In view of the foregoing background, the present disclosure provides a technique for reducing the chances of the differential amplifier and the semiconductor memory device operating erroneously.